The invention is directed to an integrated circuit having an anti latch-up circuit in complementary MOS circuit technology conforming to the preamble of patent claim 1.
In integrated circuits of this species in complementary MOS technology, parasitic pnpn paths between the supply voltage (V.sub.DD) and the ground (V.sub.ss) occur that are similar to a thyristor. This parasitic four-layer structure can be triggered by disturbances, for example by current pulses or by over-shoots or under-shoots of the applied supply voltage at the semiconductor layers. The change from the normal condition into a highly conductive condition, i.e. the triggering of this four-layer structure, is referred to as latch-up.
For understanding the latch-up effect, it can be assumed that four successive semiconductor layers of alternating conductivities are generally present between a terminal of a field effect transistor of the first channel type lying in a well-shaped semiconductor zone and a terminal of a field effect transistor of the second channel type placed outside of this zone on the semiconductor substrate, whereby the one terminal region of the former transistor forms the first semiconductor layer, the well-shaped semiconductor zone forms the second semiconductor layer, the semiconductor substrate forms the third semiconductor layer and the one terminal region of the latter transistor forms the fourth semiconductor layer. A parasitic, bipolar pnp transistor and an npn transistor derive due to this structure. The collector of the pnp transistor corresponds to the base of the npn transistor and the base of the pnp transistor corresponds to the collector of the npn transistor. This structure forms a four-layer diode having the layer sequence pnpn as in a thyristor. Given a positive bias of the semiconductor substrate, the pn-junction between the third and fourth semiconductor layers can be biased to such an extent in conducting direction that a current path that is to be attributed to a parasitic thyristor effect within this four-layer structure arises between the said transistor terminals. The current path then continues to be present after a dismantlying of the positive substrate bias and can thermally overload the integrated circuit.
The latch-up effect is described in the textbook Halbleiterelektronik 14, H. Weiss, K. Horninger, "Integrierte MOS-Schaltungen", pages 109-112. A modification of the technology (doping profiles) or measures in the design (well spacings) are proposed here as alleviation. Another solution for suppressing the latch-up effect triggered by substrate/shift currents (for example, upon turn-on) is presented in the publication by D. Takacs et al, "Static and transient latch-up hardness in n-well CMOS with on-chip substrate bias generator", IEDM 85, Technical Digest, pages 504-508. A clamp circuit is proposed therein that prevents a latch-up effect in that the semiconductor substrate potential is limited to a value that is not adequate for activating the parasitic bipolar transistors in the semiconductor substrate. To that end, the clamp circuit must carry the high capacitative charging currents off to ground.
Another possibility of suppressing the latch-up effect produced by over-shoots/under-shoots at the input/output terminals lies in the employment of Schottky contacts that are wired between the source/drain terminals of the field effect transistors and the semiconductor substrate or the well-shaped semiconductor zone. Such an arrangement may be derived from FIGS. 2 and 3 in the publication, IEEE Transaction on Electron Devices, Vol. ED-32, No. 2, February 1985, pages 194-202, "A VLSI Suitable Schottky-Barrier CMOS Process" by S. E. Swirhun et al. FIG. 2A thereby shows an inverter that is equipped with Schottky contacts in an n-shaped semiconductor zone, these Schottky contacts being fashioned of platinum-silicon (PtSi) at the source and drain terminals of a MOS transistor. FIG. 3A of the above-recited publication shows buried Schottky contacts at the source and drain terminals of a MOS transistor as well in a well-shaped semiconductor zone. These contacts are arranged such that they form an ohmic contact in lateral direction and form a Schottky contact for the current flow in vertical direction.
A deterioration of the MOS transistor parameters and Schottky stray currents can arise due to the introduction of the Schottky contacts as proposed in the publication of IEEE Transactions. Moreover, the introduction of these Schottky contacts requires an involved process management. The possibility of the positive charging of the semiconductor substrate is not fundamentally excluded by a clamp circuit as recited in the publication of D. Takacs et al; rather, the influences thereof are merely compensated in that a low-impedance ground connection in turn dismantles the positive charging in case a positive charging of the semiconductor substrate has occurred.